[PATCH] D86294: [RFC] AMDGPU/GlobalISel: Look through copies in GIM_CheckOpcode and add post-isel hook

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4535
+void SIInstrInfo::AdjustInstrPostInstrSelectionBase(
+    MachineInstr &MI, SDNode *Node, const SIRegisterInfo *TRI) const {
+  MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
----------------
Forcing a function to be shared that refers to an SDNode is also pretty awkward


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4538
+
+  if (isVOP3(MI.getOpcode())) {
+    // Make sure constant bus requirements are respected.
----------------
I was trying to avoid doing things this way. This is selecting instructions incorrectly, and then relying on something else to fix them up. I think we should select trivially correct instructions, and a follow on pass could do a better job figuring out the optimal SGPR operands. This is why RegBankSelect is forcing everything to VGPRs for VALU instructions. The later pass will have an easier time if everything is expected to consistently be in VGPRs, rather than having to figure out if some operands are already scalar and moving them back to VGPRs if it decided another copy was better


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86294/new/

https://reviews.llvm.org/D86294