[PATCH] D86225: [AArch64] Optimize instruction selection for certain vector shuffles

[Mikhail Maltsev via Phabricator via llvm-commits]

miyuki created this revision.
miyuki added reviewers: ostannard, dmgreen, simon_tatham, samparker.
Herald added subscribers: llvm-commits, danielkiss, steven.zhang, hiraditya, kristof.beyls.
Herald added a project: LLVM.
miyuki requested review of this revision.

This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.

For example:

  shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>

is essentially:

  shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>

Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D86225

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-2velem.ll
  llvm/test/CodeGen/AArch64/arm64-vext_reverse.ll
  llvm/test/CodeGen/AArch64/neon-extract.ll
  llvm/test/CodeGen/AArch64/neon-wide-splat.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization-nan.ll

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