[PATCH] D82496: [amdgpu] Add codegen support for HIP dynamic shared memory.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:2230-2231
+          // Adjust alignment for that dynamic shared memory array.
+          MFI->setDynLDSAlign(
+              B.getDataLayout().getABITypeAlign(ATy->getElementType()));
+          LLT S32 = LLT::scalar(32);
----------------
hliao wrote:
> arsenm wrote:
> > Should use the aggregate alignment, not the element
> Propose to add `preFinalizeLowering` before pseudo instruction expansion so that both GISel and DAGISel have the chance to adjust LDS size.
It's really cleaner to just have this compute what you care about at the point you care about it. Having a point where this needs to be made consistent is both worse from a serialization perspective, and from an optimization point since theoretically we could spill into the padding later


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  https://reviews.llvm.org/D82496/new/

https://reviews.llvm.org/D82496