[PATCH] D84641: AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir:140-141
+    ; Test without already assigned register class
+    %4:vgpr(s16) = G_FCONSTANT half 1.0
+    %5:vgpr(s16) = G_FCONSTANT half 8.0
     $vgpr0 = COPY %2
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foad wrote:
> I'm confused - how are these lines testing anything different than lines 134-135?
The %2, %3 cases already worked because they have uses on the copy instruction, which constrained the source register class so this worked. The %4/%5 cases do not have uses that will be constrained to a regclass, so this would hit the broken path for getting the register size


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  https://reviews.llvm.org/D84641/new/

https://reviews.llvm.org/D84641