[PATCH] D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> v2i32 and v4i64 do not have NEON support, so I mapped those to scalable vectors. Is that the correct thing to do?

Makes sense to me.

> How do we want to handle i8/i16 vectors? Shall we sign extend to i32 vectors, then truncate the result?

We have code to do this for scalable types in AArch64TargetLowering::LowerDIV; I think it makes sense to extend it to fixed types.  We can leave this for a followup, though.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1140
+    setOperationAction(ISD::SDIV, VT, Custom);
+    setOperationAction(ISD::UDIV, VT, Custom);
+  }
----------------
Did you mean to add udiv testcases?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D85982/new/

https://reviews.llvm.org/D85982