[PATCH] D85982: [SVE] Lower fixed length vXi32/vXi64 SDIV

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: paulwalker-arm, efriedma, david-arm.
Herald added subscribers: llvm-commits, psnobl, hiraditya, tschuett.
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cameron.mcinally requested review of this revision.

Here's a patch to lower SDIV for vectors of i32/i64 to scalable vectors.

And a couple follow-up questions:

1. v2i32 and v4i64 do not have NEON support, so I mapped those to scalable vectors. Is that the correct thing to do?

2. How do we want to handle i8/i16 vectors? Shall we sign extend to i32 vectors, then truncate the result?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85982

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll

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