[PATCH] D85767: [AMDGPU] Spill register and offset register cannot be same

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/frame-pointer-spill.mir:6-45
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
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You don't need most of these fields, probably just the stack related ones in machineFunctionInfo and tracksRegLiveness


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Comment at: llvm/test/CodeGen/AMDGPU/frame-pointer-spill.mir:46
+  highBitsOf32BitAddress: 0
+stack:
+  - { id: 0, name: '', type: default, offset: 0, size: 16, 
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Why do you need so many stack objects? Can you just add one artificial object that's big enough to force the huge frame?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85767/new/

https://reviews.llvm.org/D85767