[llvm] cc892fd - [VectorCombine] early exit if target has no vector registers

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-08-12T09:22:31-04:00
New Revision: cc892fd9f4cb7ad8c6b37bc260fd12c2edf3745d

URL: https://github.com/llvm/llvm-project/commit/cc892fd9f4cb7ad8c6b37bc260fd12c2edf3745d
DIFF: https://github.com/llvm/llvm-project/commit/cc892fd9f4cb7ad8c6b37bc260fd12c2edf3745d.diff

LOG: [VectorCombine] early exit if target has no vector registers

Based on post-commit discussion in:
D81766

Other vectorization passes (SLP and Loop) use this TTI API similarly.

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/VectorCombine.cpp
    llvm/test/Transforms/VectorCombine/X86/no-sse.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 7faba73abf0f..03fdda093584 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -670,6 +670,10 @@ bool VectorCombine::run() {
   if (DisableVectorCombine)
     return false;
 
+  // Don't attempt vectorization if the target does not support vectors.
+  if (!TTI.getNumberOfRegisters(TTI.getRegisterClassForType(/*Vector*/ true)))
+    return false;
+
   bool MadeChange = false;
   for (BasicBlock &BB : F) {
     // Ignore unreachable basic blocks.

diff  --git a/llvm/test/Transforms/VectorCombine/X86/no-sse.ll b/llvm/test/Transforms/VectorCombine/X86/no-sse.ll
index ccf0e0d29df7..bd1806b0f1f9 100644
--- a/llvm/test/Transforms/VectorCombine/X86/no-sse.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/no-sse.ll
@@ -1,9 +1,12 @@
-; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s --check-prefixes=CHECK
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s
+
+; Don't spend time on vector transforms if the target does not support vectors.
 
 define <4 x float> @bitcast_shuf_same_size(<4 x i32> %v) {
 ; CHECK-LABEL: @bitcast_shuf_same_size(
-; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[V:%.*]] to <4 x float>
-; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <4 x float>
 ; CHECK-NEXT:    ret <4 x float> [[R]]
 ;
   %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>