[llvm] 89a7f64 - [VectorCombine] add test for x86 target with SSE disabled; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2020-08-12T09:22:31-04:00
New Revision: 89a7f64afc7968ef3337472d02f7e08681f1766e

URL: https://github.com/llvm/llvm-project/commit/89a7f64afc7968ef3337472d02f7e08681f1766e
DIFF: https://github.com/llvm/llvm-project/commit/89a7f64afc7968ef3337472d02f7e08681f1766e.diff

LOG: [VectorCombine] add test for x86 target with SSE disabled; NFC

Added: 
    llvm/test/Transforms/VectorCombine/X86/no-sse.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/Transforms/VectorCombine/X86/no-sse.ll b/llvm/test/Transforms/VectorCombine/X86/no-sse.ll
new file mode 100644
index 000000000000..ccf0e0d29df7
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/no-sse.ll
@@ -0,0 +1,12 @@
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s --check-prefixes=CHECK
+
+define <4 x float> @bitcast_shuf_same_size(<4 x i32> %v) {
+; CHECK-LABEL: @bitcast_shuf_same_size(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[V:%.*]] to <4 x float>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r = bitcast <4 x i32> %shuf to <4 x float>
+  ret <4 x float> %r
+}