[PATCH] D81766: [VectorCombine] try to create vector loads from scalar loads

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In D81766#2211936 <https://reviews.llvm.org/D81766#2211936>, @srj wrote:

> Update: it appears that `VectorSize` (from `TTI.getMinVectorRegisterBitWidth()`) is zero in this case, which causes the assertion failure.
>
> This appears to be the case because `HexagonTTIImpl::getMinVectorRegisterBitWidth()` returns `0` if `useHVX()` isn't true... and `useHVX()` returns false if the `HexagonAutoHVX` option isn't enabled.
>
> By design, Halide doesn't enable the `HexagonAutoHVX` option; we like to do all the vectorization ourselves.
>
> I'm not sure how to resolve this issue -- the flaw here seems to lie in `HexagonTTIImpl`'s assumption that disabling `HexagonAutoHVX` should cause it to report zero-width vectors, which seems to be a dubious decision (and one that is at odds with every other implementation of `getMinVectorRegisterBitWidth()` that I see in trunk LLVM (none of them appear to ever return 0).
>
> Would it make sense to consider backing out this change until this can be resolved, since it clearly appears to have bad consequences for Hexagon/HVX codegen?

Can we just add another condition (!VectorSize) to this bailout?
if (!ScalarSize || VectorSize % ScalarSize != 0)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81766/new/

https://reviews.llvm.org/D81766