[PATCH] D81766: [VectorCombine] try to create vector loads from scalar loads

[Steven Johnson via Phabricator via llvm-commits]

srj added a comment.

Update: it appears that `VectorSize` (from `TTI.getMinVectorRegisterBitWidth()`) is zero in this case, which causes the assertion failure.

This appears to be the case because `HexagonTTIImpl::getMinVectorRegisterBitWidth()` returns `0` if `useHVX()` isn't true... and `useHVX()` returns false if the `HexagonAutoHVX` option isn't enabled.

By design, Halide doesn't enable the `HexagonAutoHVX` option; we like to do all the vectorization ourselves.

I'm not sure how to resolve this issue -- the flaw here seems to lie in `HexagonTTIImpl`'s assumption that disabling `HexagonAutoHVX` should cause it to report zero-width vectors, which seems to be a dubious decision (and one that is at odds with every other implementation of `getMinVectorRegisterBitWidth()` that I see in trunk LLVM (none of them appear to ever return 0).

Would it make sense to consider backing out this change until this can be resolved, since it clearly appears to have bad consequences for Hexagon/HVX codegen?


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  https://reviews.llvm.org/D81766/new/

https://reviews.llvm.org/D81766