[PATCH] D82788: [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 10 12:11:19 PDT 2020
arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.
================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1397-1398
+ // disabled.
+ if (Subtarget->hasUnalignedDSAccess() &&
+ Subtarget->hasUnalignedAccessMode()) {
+ if (IsFast)
----------------
We should do something to avoid every user needing to consider both ModeEnabled && ModeWorks. You can leave that for the later cleanup patch though; either you can move this combination check into a helper method, or somehow make the lack of hardware support imply the mode is disabled
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82788/new/
https://reviews.llvm.org/D82788
More information about the llvm-commits
mailing list