[PATCH] D85234: [AMDGPU] Scavenge temp reg for AGPR spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:824
+        if (TmpReg == AMDGPU::NoRegister) {
+          // FIXME: change to scavengeRegisterBackwards()
+          TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
----------------
Should assert on RS in case this ever gets called from PEI and we didn't enable the scavenger


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85234/new/

https://reviews.llvm.org/D85234