[PATCH] D85234: [AMDGPU] Scavenge temp reg for AGPR spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:674
 
-multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> {
+multiclass SI_SPILL_VGPR <RegisterClass vgpr_class, bit UsesTmp = 0> {
   let UseNamedOperandTable = 1, VGPRSpill = 1,
----------------
Can you add a comment explaining UsesTmp? It took me a minute to figure out what the point of this was. Is this accounting for the waitcnts and overly large frame offsets too?

I'm not sure it's super important to get this perfect, since BranchRelaxation runs after this but it doesn't hurt to be conservative here


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:823
+      if (hasAGPRs(RC)) {
+        if (TmpReg == AMDGPU::NoRegister) {
+          // FIXME: change to scavengeRegisterBackwards()
----------------
!TmpReg


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Comment at: llvm/test/CodeGen/AMDGPU/spill-agpr.mir:58
+---
+name: spill_restore_agpr64
+tracksRegLiveness: true
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FYI I have a patch to fix 96-bit spills


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85234/new/

https://reviews.llvm.org/D85234