[PATCH] D85366: [RISCV] Disparage CSR instructions

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

Have you seen this actually occur? The fact that `hasSideEffects` is set surely means that it cannot possibly be duplicated, nor scheduled out-of-order with other side-effect-affected instructions? Also, the only CSR instructions that currently get generated _by CodeGen_ are reads of cycle[h], which are very well-behaved. Naive implementations might still take a slow path just because they're CSR instructions, but it'd be very easy microarchitecturally to quickly read the cycle counter in an ALU as if it were just a normal GPR move. In such cases you really would want to be able to express scheduling information for it just like other arithmetic operations.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D85366/new/

https://reviews.llvm.org/D85366