[PATCH] D85366: [RISCV] Disparage CSR instructions

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

LGTM!

Given the comment on `isBarrier` in Target.td, I'm not sure it applies: `bit isBarrier = 0; // Can control flow fall through this instruction?`


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85366/new/

https://reviews.llvm.org/D85366