[llvm] e7a8ee0 - [AMDGPU] Regenerate tests to fix whitespace indentations
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 2 10:11:30 PDT 2020
Author: Simon Pilgrim
Date: 2020-08-02T18:11:18+01:00
New Revision: e7a8ee00e6c3b20fc04792db1acf9d5324a1b7bb
URL: https://github.com/llvm/llvm-project/commit/e7a8ee00e6c3b20fc04792db1acf9d5324a1b7bb
DIFF: https://github.com/llvm/llvm-project/commit/e7a8ee00e6c3b20fc04792db1acf9d5324a1b7bb.diff
LOG: [AMDGPU] Regenerate tests to fix whitespace indentations
Noticed while updating D77804
Added:
Modified:
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
llvm/test/CodeGen/AMDGPU/fshr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 7ea072bffecb..f520b4a8fd8f 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -636,81 +636,81 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)
define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
; SI-LABEL: load_v4i8_to_v4f32_2_uses:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
-; SI-NEXT: s_mov_b32 s11, 0xf000
-; SI-NEXT: s_mov_b32 s2, 0
-; SI-NEXT: s_mov_b32 s3, s11
-; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v4, v[0:1], s[0:3], 0 addr64
-; SI-NEXT: s_mov_b32 s10, -1
-; SI-NEXT: s_movk_i32 s0, 0xff
-; SI-NEXT: s_mov_b32 s6, s10
-; SI-NEXT: s_mov_b32 s7, s11
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
-; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
-; SI-NEXT: v_and_b32_e32 v7, 0xff00, v4
-; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
-; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
-; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
-; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
-; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_and_b32_e32 v0, s0, v4
-; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5
-; SI-NEXT: v_or_b32_e32 v0, v7, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
-; SI-NEXT: v_and_b32_e32 v2, s0, v2
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
-; SI-NEXT: v_or_b32_e32 v1, v1, v2
-; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; SI-NEXT: v_or_b32_e32 v0, v1, v0
-; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
-; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s11, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: s_mov_b32 s3, s11
+; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v4, v[0:1], s[0:3], 0 addr64
+; SI-NEXT: s_mov_b32 s10, -1
+; SI-NEXT: s_movk_i32 s0, 0xff
+; SI-NEXT: s_mov_b32 s6, s10
+; SI-NEXT: s_mov_b32 s7, s11
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; SI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
+; SI-NEXT: v_and_b32_e32 v7, 0xff00, v4
+; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
+; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
+; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
+; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_and_b32_e32 v0, s0, v4
+; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5
+; SI-NEXT: v_or_b32_e32 v0, v7, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v6
+; SI-NEXT: v_and_b32_e32 v2, s0, v2
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
+; SI-NEXT: v_or_b32_e32 v1, v1, v2
+; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; SI-NEXT: v_or_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
+; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; SI-NEXT: s_endpgm
;
; VI-LABEL: load_v4i8_to_v4f32_2_uses:
; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
-; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
-; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; VI-NEXT: s_mov_b32 s11, 0xf000
-; VI-NEXT: s_mov_b32 s10, -1
-; VI-NEXT: v_mov_b32_e32 v5, 9
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_dword v4, v[0:1]
-; VI-NEXT: s_mov_b32 s6, s10
-; VI-NEXT: s_mov_b32 s7, s11
-; VI-NEXT: s_movk_i32 s0, 0x900
-; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
-; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
-; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
-; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; VI-NEXT: v_and_b32_e32 v7, 0xffffff00, v4
-; VI-NEXT: v_add_u16_e32 v8, 9, v4
-; VI-NEXT: v_add_u16_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v6
-; VI-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: v_add_u16_e32 v0, s0, v0
-; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
-; VI-NEXT: s_endpgm
+; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 s11, 0xf000
+; VI-NEXT: s_mov_b32 s10, -1
+; VI-NEXT: v_mov_b32_e32 v5, 9
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dword v4, v[0:1]
+; VI-NEXT: s_mov_b32 s6, s10
+; VI-NEXT: s_mov_b32 s7, s11
+; VI-NEXT: s_movk_i32 s0, 0x900
+; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
+; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
+; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
+; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; VI-NEXT: v_and_b32_e32 v7, 0xffffff00, v4
+; VI-NEXT: v_add_u16_e32 v8, 9, v4
+; VI-NEXT: v_add_u16_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v6
+; VI-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT: v_mov_b32_e32 v2, s0
+; VI-NEXT: v_add_u16_e32 v0, s0, v0
+; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; VI-NEXT: s_endpgm
%tid.x = call i32 @llvm.amdgcn.workitem.id.x()
%in.ptr = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid.x
%load = load <4 x i8>, <4 x i8> addrspace(1)* %in.ptr, align 4
@@ -725,42 +725,42 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* n
define amdgpu_kernel void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
; SI-LABEL: load_v7i8_to_v7f32:
; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s2, 0
-; SI-NEXT: s_mov_b32 s3, s7
-; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
-; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
-; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2
-; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:3
-; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:4
-; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:5
-; SI-NEXT: buffer_load_ubyte v8, v[0:1], s[0:3], 0 addr64 offset:6
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_waitcnt vmcnt(6)
-; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_cvt_f32_ubyte2_e32 v1, v3
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v4
-; SI-NEXT: v_or_b32_e32 v3, v9, v6
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_cvt_f32_ubyte2_e32 v5, v5
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v8
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:24
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v7
-; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v2
-; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v2
-; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s2, 0
+; SI-NEXT: s_mov_b32 s3, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[0:3], 0 addr64
+; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[0:3], 0 addr64 offset:1
+; SI-NEXT: buffer_load_ubyte v6, v[0:1], s[0:3], 0 addr64 offset:2
+; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[0:3], 0 addr64 offset:3
+; SI-NEXT: buffer_load_ubyte v7, v[0:1], s[0:3], 0 addr64 offset:4
+; SI-NEXT: buffer_load_ubyte v5, v[0:1], s[0:3], 0 addr64 offset:5
+; SI-NEXT: buffer_load_ubyte v8, v[0:1], s[0:3], 0 addr64 offset:6
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_waitcnt vmcnt(6)
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_cvt_f32_ubyte2_e32 v1, v3
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v4
+; SI-NEXT: v_or_b32_e32 v3, v9, v6
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_cvt_f32_ubyte2_e32 v5, v5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v8
+; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:24
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; SI-NEXT: v_cvt_f32_ubyte0_e32 v4, v7
+; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v2
+; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v2
+; SI-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_endpgm
;
; VI-LABEL: load_v7i8_to_v7f32:
; VI: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fshr.ll b/llvm/test/CodeGen/AMDGPU/fshr.ll
index 444421443b4f..bacbfcb8f500 100644
--- a/llvm/test/CodeGen/AMDGPU/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshr.ll
@@ -1210,167 +1210,167 @@ define i24 @v_fshr_i24(i24 %src0, i24 %src1, i24 %src2) {
define <2 x i24> @v_fshr_v2i24(<2 x i24> %src0, <2 x i24> %src1, <2 x i24> %src2) {
; SI-LABEL: v_fshr_v2i24:
; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
-; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
-; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
-; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32
-; SI-NEXT: s_mov_b32 s4, 0xffffff
-; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
-; SI-NEXT: v_add_i32_e32 v8, vcc, 4, v0
-; SI-NEXT: v_add_i32_e32 v9, vcc, 5, v0
-; SI-NEXT: v_add_i32_e32 v10, vcc, 2, v0
-; SI-NEXT: s_waitcnt vmcnt(5)
-; SI-NEXT: v_and_b32_e32 v14, s4, v1
-; SI-NEXT: s_waitcnt vmcnt(4)
-; SI-NEXT: v_and_b32_e32 v2, s4, v2
-; SI-NEXT: v_mul_hi_u32 v12, v2, s5
-; SI-NEXT: s_waitcnt vmcnt(3)
-; SI-NEXT: v_and_b32_e32 v3, s4, v3
-; SI-NEXT: v_mul_hi_u32 v13, v3, s5
-; SI-NEXT: s_waitcnt vmcnt(1)
-; SI-NEXT: v_and_b32_e32 v11, s4, v5
-; SI-NEXT: v_lshrrev_b32_e32 v12, 4, v12
-; SI-NEXT: v_mul_lo_u32 v12, v12, 24
-; SI-NEXT: v_lshrrev_b32_e32 v13, 4, v13
-; SI-NEXT: v_mul_lo_u32 v13, v13, 24
-; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v12
-; SI-NEXT: v_lshr_b32_e32 v12, v14, v2
-; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v13
-; SI-NEXT: v_sub_i32_e32 v13, vcc, 24, v2
-; SI-NEXT: v_sub_i32_e32 v14, vcc, 24, v3
-; SI-NEXT: v_and_b32_e32 v13, s4, v13
-; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_lshl_b32_e32 v6, v6, v13
-; SI-NEXT: v_and_b32_e32 v14, 0xffffff, v14
-; SI-NEXT: v_lshr_b32_e32 v11, v11, v3
-; SI-NEXT: v_lshl_b32_e32 v4, v4, v14
-; SI-NEXT: v_or_b32_e32 v6, v6, v12
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; SI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; SI-NEXT: v_or_b32_e32 v4, v4, v11
-; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; SI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen
-; SI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
-; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v2
-; SI-NEXT: s_waitcnt expcnt(1)
-; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; SI-NEXT: s_waitcnt expcnt(0)
-; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; SI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen
-; SI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen
-; SI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
+; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
+; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
+; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32
+; SI-NEXT: s_mov_b32 s4, 0xffffff
+; SI-NEXT: s_mov_b32 s5, 0xaaaaaaab
+; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v0
+; SI-NEXT: v_add_i32_e32 v8, vcc, 4, v0
+; SI-NEXT: v_add_i32_e32 v9, vcc, 5, v0
+; SI-NEXT: v_add_i32_e32 v10, vcc, 2, v0
+; SI-NEXT: s_waitcnt vmcnt(5)
+; SI-NEXT: v_and_b32_e32 v14, s4, v1
+; SI-NEXT: s_waitcnt vmcnt(4)
+; SI-NEXT: v_and_b32_e32 v2, s4, v2
+; SI-NEXT: v_mul_hi_u32 v12, v2, s5
+; SI-NEXT: s_waitcnt vmcnt(3)
+; SI-NEXT: v_and_b32_e32 v3, s4, v3
+; SI-NEXT: v_mul_hi_u32 v13, v3, s5
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_and_b32_e32 v11, s4, v5
+; SI-NEXT: v_lshrrev_b32_e32 v12, 4, v12
+; SI-NEXT: v_mul_lo_u32 v12, v12, 24
+; SI-NEXT: v_lshrrev_b32_e32 v13, 4, v13
+; SI-NEXT: v_mul_lo_u32 v13, v13, 24
+; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v12
+; SI-NEXT: v_lshr_b32_e32 v12, v14, v2
+; SI-NEXT: v_sub_i32_e32 v3, vcc, v3, v13
+; SI-NEXT: v_sub_i32_e32 v13, vcc, 24, v2
+; SI-NEXT: v_sub_i32_e32 v14, vcc, 24, v3
+; SI-NEXT: v_and_b32_e32 v13, s4, v13
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_lshl_b32_e32 v6, v6, v13
+; SI-NEXT: v_and_b32_e32 v14, 0xffffff, v14
+; SI-NEXT: v_lshr_b32_e32 v11, v11, v3
+; SI-NEXT: v_lshl_b32_e32 v4, v4, v14
+; SI-NEXT: v_or_b32_e32 v6, v6, v12
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; SI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; SI-NEXT: v_or_b32_e32 v4, v4, v11
+; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; SI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; SI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen
+; SI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
+; SI-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; SI-NEXT: s_waitcnt expcnt(1)
+; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; SI-NEXT: s_waitcnt expcnt(0)
+; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; SI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen
+; SI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen
+; SI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
+; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_fshr_v2i24:
; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
-; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
-; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
-; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
-; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32
-; VI-NEXT: s_mov_b32 s4, 0xffffff
-; VI-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v0
-; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0
-; VI-NEXT: v_add_u32_e32 v9, vcc, 5, v0
-; VI-NEXT: v_add_u32_e32 v10, vcc, 2, v0
-; VI-NEXT: s_waitcnt vmcnt(5)
-; VI-NEXT: v_and_b32_e32 v14, s4, v1
-; VI-NEXT: s_waitcnt vmcnt(4)
-; VI-NEXT: v_and_b32_e32 v2, s4, v2
-; VI-NEXT: v_mul_hi_u32 v12, v2, s5
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_and_b32_e32 v3, s4, v3
-; VI-NEXT: v_mul_hi_u32 v13, v3, s5
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_and_b32_e32 v11, s4, v5
-; VI-NEXT: v_lshrrev_b32_e32 v12, 4, v12
-; VI-NEXT: v_mul_lo_u32 v12, v12, 24
-; VI-NEXT: v_lshrrev_b32_e32 v13, 4, v13
-; VI-NEXT: v_mul_lo_u32 v13, v13, 24
-; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v12
-; VI-NEXT: v_lshrrev_b32_e32 v12, v2, v14
-; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v13
-; VI-NEXT: v_sub_u32_e32 v13, vcc, 24, v2
-; VI-NEXT: v_sub_u32_e32 v14, vcc, 24, v3
-; VI-NEXT: v_and_b32_e32 v13, s4, v13
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v6, v13, v6
-; VI-NEXT: v_and_b32_e32 v14, 0xffffff, v14
-; VI-NEXT: v_lshrrev_b32_e32 v11, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, v14, v4
-; VI-NEXT: v_or_b32_e32 v6, v6, v12
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
-; VI-NEXT: v_or_b32_e32 v4, v4, v11
-; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
-; VI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen
-; VI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v2
-; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; VI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen
-; VI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen
-; VI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
+; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:20
+; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
+; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32
+; VI-NEXT: s_mov_b32 s4, 0xffffff
+; VI-NEXT: s_mov_b32 s5, 0xaaaaaaab
+; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v0
+; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0
+; VI-NEXT: v_add_u32_e32 v9, vcc, 5, v0
+; VI-NEXT: v_add_u32_e32 v10, vcc, 2, v0
+; VI-NEXT: s_waitcnt vmcnt(5)
+; VI-NEXT: v_and_b32_e32 v14, s4, v1
+; VI-NEXT: s_waitcnt vmcnt(4)
+; VI-NEXT: v_and_b32_e32 v2, s4, v2
+; VI-NEXT: v_mul_hi_u32 v12, v2, s5
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_and_b32_e32 v3, s4, v3
+; VI-NEXT: v_mul_hi_u32 v13, v3, s5
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_and_b32_e32 v11, s4, v5
+; VI-NEXT: v_lshrrev_b32_e32 v12, 4, v12
+; VI-NEXT: v_mul_lo_u32 v12, v12, 24
+; VI-NEXT: v_lshrrev_b32_e32 v13, 4, v13
+; VI-NEXT: v_mul_lo_u32 v13, v13, 24
+; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v12
+; VI-NEXT: v_lshrrev_b32_e32 v12, v2, v14
+; VI-NEXT: v_sub_u32_e32 v3, vcc, v3, v13
+; VI-NEXT: v_sub_u32_e32 v13, vcc, 24, v2
+; VI-NEXT: v_sub_u32_e32 v14, vcc, 24, v3
+; VI-NEXT: v_and_b32_e32 v13, s4, v13
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v6, v13, v6
+; VI-NEXT: v_and_b32_e32 v14, 0xffffff, v14
+; VI-NEXT: v_lshrrev_b32_e32 v11, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, v14, v4
+; VI-NEXT: v_or_b32_e32 v6, v6, v12
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; VI-NEXT: v_or_b32_e32 v4, v4, v11
+; VI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
+; VI-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc
+; VI-NEXT: buffer_store_byte v2, v7, s[0:3], 0 offen
+; VI-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshrrev_b32_e32 v0, 8, v2
+; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; VI-NEXT: buffer_store_byte v0, v8, s[0:3], 0 offen
+; VI-NEXT: buffer_store_byte v2, v9, s[0:3], 0 offen
+; VI-NEXT: buffer_store_byte v1, v10, s[0:3], 0 offen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
-; GFX9-NEXT: s_mov_b32 s4, 0xffffff
-; GFX9-NEXT: s_mov_b32 s5, 0xaaaaaaab
-; GFX9-NEXT: s_waitcnt vmcnt(5)
-; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
-; GFX9-NEXT: v_mul_hi_u32 v6, v1, s5
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_and_b32_e32 v2, s4, v2
-; GFX9-NEXT: v_mul_hi_u32 v7, v2, s5
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_and_b32_e32 v9, s4, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 4, v6
-; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 4, v7
-; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v10, s4, v8
-; GFX9-NEXT: v_sub_u32_e32 v1, v1, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, v1, v10
-; GFX9-NEXT: v_sub_u32_e32 v2, v2, v7
-; GFX9-NEXT: v_sub_u32_e32 v7, 24, v1
-; GFX9-NEXT: v_sub_u32_e32 v10, 24, v2
-; GFX9-NEXT: v_and_b32_e32 v7, s4, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, v2, v9
-; GFX9-NEXT: v_and_b32_e32 v10, 0xffffff, v10
-; GFX9-NEXT: v_lshl_or_b32 v5, v5, v7, v6
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, v10, v9
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v2
-; GFX9-NEXT: buffer_store_byte_d16_hi v2, v0, s[0:3], 0 offen offset:5
-; GFX9-NEXT: buffer_store_byte v3, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: buffer_store_byte v2, v0, s[0:3], 0 offen offset:3
-; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], 0 offen offset:2
-; GFX9-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:8
+; GFX9-NEXT: s_mov_b32 s4, 0xffffff
+; GFX9-NEXT: s_mov_b32 s5, 0xaaaaaaab
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_and_b32_e32 v1, s4, v1
+; GFX9-NEXT: v_mul_hi_u32 v6, v1, s5
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_and_b32_e32 v2, s4, v2
+; GFX9-NEXT: v_mul_hi_u32 v7, v2, s5
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_and_b32_e32 v9, s4, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 4, v6
+; GFX9-NEXT: v_mul_lo_u32 v6, v6, 24
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 4, v7
+; GFX9-NEXT: v_mul_lo_u32 v7, v7, 24
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v10, s4, v8
+; GFX9-NEXT: v_sub_u32_e32 v1, v1, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, v1, v10
+; GFX9-NEXT: v_sub_u32_e32 v2, v2, v7
+; GFX9-NEXT: v_sub_u32_e32 v7, 24, v1
+; GFX9-NEXT: v_sub_u32_e32 v10, 24, v2
+; GFX9-NEXT: v_and_b32_e32 v7, s4, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, v2, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffffff, v10
+; GFX9-NEXT: v_lshl_or_b32 v5, v5, v7, v6
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v8, vcc
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, v10, v9
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX9-NEXT: buffer_store_byte_d16_hi v2, v0, s[0:3], 0 offen offset:5
+; GFX9-NEXT: buffer_store_byte v3, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_store_byte v2, v0, s[0:3], 0 offen offset:3
+; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], 0 offen offset:2
+; GFX9-NEXT: buffer_store_short v1, v0, s[0:3], 0 offen
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_fshr_v2i24:
; R600: ; %bb.0:
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