[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

In D84833#2184820 <https://reviews.llvm.org/D84833#2184820>, @luismarques wrote:

> In D84833#2184534 <https://reviews.llvm.org/D84833#2184534>, @jrtc27 wrote:
>
>> Other than the TODO, yes (and hopefully you agree with my suggestions here!). I would also like to see branch-relaxation.ll grow RV64 RUN lines for completeness, even if it's probably a bit redundant (and creates a slight explosion..), but I can do that as a follow-up patch.
>
> This patch still seems to need some additional work. When I apply it and run the tests I get a crash for the `branch-relaxation.ll` test:
>
>   *** Bad machine code: MBB has unexpected successors which are not branch targets, fallthrough, EHPads, or inlineasm_br targets. ***
>   - function:    relax_jal
>   - basic block: %bb.3  (0x5621c4161a48)

Ah, that's because the TableGen definition is broken (works fine for asm, but not code gen):

  let isCall = 0, isBarrier = 0, isCodeGenOnly = 0, hasSideEffects = 0,
      mayStore = 0, mayLoad = 0 in

I _believe_ we need:

  isBranch = 1, isTerminator = 1, isBarrier = 1

?


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https://reviews.llvm.org/D84833