[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

Thu Jul 30 07:24:45 PDT 2020

luismarques added a comment.

In D84833#2184534 <https://reviews.llvm.org/D84833#2184534>, @jrtc27 wrote:

> Other than the TODO, yes (and hopefully you agree with my suggestions here!). I would also like to see branch-relaxation.ll grow RV64 RUN lines for completeness, even if it's probably a bit redundant (and creates a slight explosion..), but I can do that as a follow-up patch.

This patch still seems to need some additional work. When I apply it and run the tests I get a crash for the `branch-relaxation.ll` test:

  *** Bad machine code: MBB has unexpected successors which are not branch targets, fallthrough, EHPads, or inlineasm_br targets. ***
  - function:    relax_jal
  - basic block: %bb.3  (0x5621c4161a48)

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833