[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[msizanoen1 via Phabricator via llvm-commits]

msizanoen1 updated this revision to Diff 281568.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp


Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -384,7 +384,6 @@
 
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();
-  const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
 
   if (!isInt<32>(BrOffset))
     report_fatal_error(
@@ -394,11 +393,10 @@
   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
   // uses the same workaround).
   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
-  auto II = MBB.end();
 
-  MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
-    .addMBB(&DestBB)
-    .addReg(ScratchReg, RegState::Define | RegState::Dead);
+  MachineInstr &MI = *BuildMI(MBB, DL, get(RISCV::PseudoJump))
+                          .addReg(ScratchReg, RegState::Define | RegState::Dead)
+                          .addMBB(&DestBB);
 
   RS->enterBasicBlockEnd(MBB);
   unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,


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