[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:398
+  MachineInstr &MI =
+      *BuildMI(MBB, DL, get(RISCV::PseudoJump), ScratchReg).addMBB(&DestBB);
 
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I don't know how much it matters, but we know the register is dead here.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833