[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 requested changes to this revision.
jrtc27 added a comment.
This revision now requires changes to proceed.

Please avoid duplication. Something like this should be better in that regard, both for duplicating between the if/else branches and duplicating with the existing AUIPC-based expansions elsewhere.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:398-419
+  unsigned Scav;
+
+  if (TM.isPositionIndependent()) {
+    MBB.setLabelMustBeEmitted();
+    MachineInstr &AuipcMI = *BuildMI(MBB, II, DL, get(RISCV::AUIPC), ScratchReg)
+                                 .addMBB(&DestBB, RISCVII::MO_PCREL_HI);
+    BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833