[PATCH] D84833: Implement indirect branch generation in position independent code for the RISC-V target

[msizanoen1 via Phabricator via llvm-commits]

msizanoen1 updated this revision to Diff 281527.
msizanoen1 retitled this revision from "Implement indirect branch generation in position independent code for the RISC-V target and reorder BranchRelaxation to be run after RISCVExpandPseudo" to "Implement indirect branch generation in position independent code for the RISC-V target".

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84833/new/

https://reviews.llvm.org/D84833

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp


Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -386,9 +386,6 @@
   MachineRegisterInfo &MRI = MF->getRegInfo();
   const auto &TM = static_cast<const RISCVTargetMachine &>(MF->getTarget());
 
-  if (TM.isPositionIndependent())
-    report_fatal_error("Unable to insert indirect branch");
-
   if (!isInt<32>(BrOffset))
     report_fatal_error(
         "Branch offsets outside of the signed 32-bit range not supported");
@@ -398,16 +395,29 @@
   // uses the same workaround).
   Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
   auto II = MBB.end();
+  unsigned Scav;
+
+  if (TM.isPositionIndependent()) {
+    MBB.setLabelMustBeEmitted();
+    MachineInstr &AuipcMI = *BuildMI(MBB, II, DL, get(RISCV::AUIPC), ScratchReg)
+                                 .addMBB(&DestBB, RISCVII::MO_PCREL_HI);
+    BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
+        .addReg(ScratchReg, RegState::Kill)
+        .addMBB(&MBB, RISCVII::MO_PCREL_LO);
+    RS->enterBasicBlockEnd(MBB);
+    Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
+                                         AuipcMI.getIterator(), false, 0);
+  } else {
+    MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
+                               .addMBB(&DestBB, RISCVII::MO_HI);
+    BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
+        .addReg(ScratchReg, RegState::Kill)
+        .addMBB(&DestBB, RISCVII::MO_LO);
+    RS->enterBasicBlockEnd(MBB);
+    Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
+                                         LuiMI.getIterator(), false, 0);
+  }
 
-  MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
-                             .addMBB(&DestBB, RISCVII::MO_HI);
-  BuildMI(MBB, II, DL, get(RISCV::PseudoBRIND))
-      .addReg(ScratchReg, RegState::Kill)
-      .addMBB(&DestBB, RISCVII::MO_LO);
-
-  RS->enterBasicBlockEnd(MBB);
-  unsigned Scav = RS->scavengeRegisterBackwards(RISCV::GPRRegClass,
-                                                LuiMI.getIterator(), false, 0);
   MRI.replaceRegWith(ScratchReg, Scav);
   MRI.clearVirtRegs();
   RS->setRegUsed(Scav);


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