[PATCH] D84153: AMDGPU: Relax restriction on folding immediates into physregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:654
+    // redundant initalizations.
+    if (DestReg.isPhysical() && SrcRC->contains(DestReg))
+      return;
----------------
rampitec wrote:
> Source must be strictly scalar. You can have a copy of vector to vector (say a to v) and it can be initialized with a different mask.
> 
> In fact, how can we be sure even an SGPR was not initialized in a different CFG path? This shall never happen to a virtual register in SSA, but can easily happen to a physreg.
This is folding a constant. The mask doesn't matter. This is also not analyzing physreg defs, it's searching the uses of an SSA virtual register.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84153/new/

https://reviews.llvm.org/D84153