[PATCH] D84153: AMDGPU: Relax restriction on folding immediates into physregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

I do not think this can work with physregs given the CFG.



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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:654
+    // redundant initalizations.
+    if (DestReg.isPhysical() && SrcRC->contains(DestReg))
+      return;
----------------
Source must be strictly scalar. You can have a copy of vector to vector (say a to v) and it can be initialized with a different mask.

In fact, how can we be sure even an SGPR was not initialized in a different CFG path? This shall never happen to a virtual register in SSA, but can easily happen to a physreg.


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:658
+    const TargetRegisterClass *DestRC =
+      TRI->getRegClassForReg(*MRI, DestReg);
+    if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
----------------
This does fit into a single line.


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  https://reviews.llvm.org/D84153/new/

https://reviews.llvm.org/D84153