[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Mon Jul 27 21:45:39 PDT 2020

amyk added a comment.

Could we also elaborate in the description on how we are utilizing the new load instructions for zero extend case but not the sign extend case?

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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14197
+
+ SDValue LoadOps[] = {LD->getChain(), LD->getBasePtr(), DAG.getIntPtrConstant(MemoryType.getScalarSizeInBits(), dl)};
+
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Over 80 characters?

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Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll:5
+; RUN:   FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O0 \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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This line actually is for `-O0` and not a BE RUN line. I believe the most up to date version of the test includes the LE, BE and O0 line. 

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82502/new/

https://reviews.llvm.org/D82502