[PATCH] D84042: [AArch64][SVE] Fix alignment of last predicate callee save

Thu Jul 23 15:36:16 PDT 2020

efriedma added inline comments.

================
Comment at: llvm/test/CodeGen/AArch64/framelayout-sve.mir:376
 # CHECK: frame-setup STR_PXI killed $p4, $sp, 7
 # CHECK: $sp = frame-setup SUBXri $sp, 32, 0

----------------
It seems weird to introduce a gap in the middle of the callee-saves; I mean, the CPU doesn't care where the gap is, but it seems less readable for people.  I'd prefer to keep this as-is, and change whatever code is assuming the other layout.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84042/new/

https://reviews.llvm.org/D84042