[PATCH] D84042: [AArch64][SVE] Fix alignment of last predicate callee save

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp:2057
       case RegPairInfo::PPR:
       case RegPairInfo::ZPR:
+        if (!AArch64::PPRRegClass.contains(NextReg) &&
----------------
Since ZPRs are architecturally defined in multiplies of 16-bytes I don't see why anything needs fixing up.

At the same time I think PPRs are more problematic because they're defined in multiples of 2-bytes and thus we'd need a group of 8 to fulfil alignment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D84042/new/

https://reviews.llvm.org/D84042