[PATCH] D83818: [AArch64] fjcvtzs,rmif,cfinv,setf* all clobber nzcv

[Jon Roelofs via Phabricator via llvm-commits]

jroelofs updated this revision to Diff 280232.
jroelofs added a comment.

Add a test for the changes for fjcvtzs.

@SjoerdMeijer can you suggest a good way to write a test for the others? llvm-mc doesn't seem to have a way to print implicit defs/uses.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83818/new/

https://reviews.llvm.org/D83818

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/fjcvtzs.ll


Index: llvm/test/CodeGen/AArch64/fjcvtzs.ll
===================================================================
--- llvm/test/CodeGen/AArch64/fjcvtzs.ll
+++ llvm/test/CodeGen/AArch64/fjcvtzs.ll
@@ -1,8 +1,11 @@
 ; RUN: llc -mtriple=arm64-eabi -mattr=+jsconv -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64-eabi -mattr=+jsconv -stop-after=legalizer -o - %s | FileCheck %s --check-prefix=CHECK-MIR
 
 define i32 @test_jcvt(double %v) {
 ; CHECK-LABEL: test_jcvt:
 ; CHECK: fjcvtzs w0, d0
+; CHECK-MIR: FJCVTZS
+; CHECK-MIR-SAME: implicit-def dead $nzcv
   %val = call i32 @llvm.aarch64.fjcvtzs(double %v)
   ret i32 %val
 }
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1030,7 +1030,7 @@
 }
 
 // v8.3a floating point conversion for javascript
-let Predicates = [HasJS, HasFPARMv8] in
+let Predicates = [HasJS, HasFPARMv8], Defs = [NZCV] in
 def FJCVTZS  : BaseFPToIntegerUnscaled<0b01, 0b11, 0b110, FPR64, GPR32,
                                       "fjcvtzs",
                                       [(set GPR32:$Rd,
@@ -1039,7 +1039,7 @@
 } // HasJS, HasFPARMv8
 
 // v8.4 Flag manipulation instructions
-let Predicates = [HasFMI] in {
+let Predicates = [HasFMI], Defs = [NZCV], Uses = [NZCV] in {
 def CFINV : SimpleSystemI<0, (ins), "cfinv", "">, Sched<[WriteSys]> {
   let Inst{20-5} = 0b0000001000000000;
 }
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -1939,6 +1939,7 @@
     : I<(outs), iops, asm, ops, "", []>,
       Sched<[WriteI, ReadI, ReadI]> {
   let Uses = [NZCV];
+  let Defs = [NZCV];
   bits<5> Rn;
   let Inst{31}    = sf;
   let Inst{30-15} = 0b0111010000000000;


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