[PATCH] D84227: [ARM] Fix Asm/Disasm of TBB/TBH instructions

[David Spickett via Phabricator via llvm-commits]

DavidSpickett added a reviewer: ostannard.
DavidSpickett marked an inline comment as done.
DavidSpickett added inline comments.


================
Comment at: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:10601
     break;
+  case ARM::t2TBB:
+  case ARM::t2TBH:
----------------
There is a similar register class "rGPR" but this also removes the PC, which is allowed here. Everything else that had a register like this tells you to use arm mode when you need SP, but tbb/tbh don't have arm encodings.

Seems like it would be a common thing but I couldn't find any other instructions like this.


Repository:
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  https://reviews.llvm.org/D84227/new/

https://reviews.llvm.org/D84227