[PATCH] D81647: MIR Statepoint refactoring. Part 3: Spill GC Ptr regs.

[Serguei Katkov via Phabricator via llvm-commits]

skatkov added inline comments.


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Comment at: llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp:276
+                          << printMBBReference(*EHPad));
+        return FI;
+      }
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assert that frame slot is reserved? (nobody used it)


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Comment at: llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp:327
+// statepoints.
+static bool hasRegReload(Register Reg, int FI, MachineBasicBlock *MBB,
+                         const TargetInstrInfo *TII,
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Can we just track for each EhPad what registers were reloaded instead of this search?


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Comment at: llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp:400
     SmallSet<Register, 8> VisitedRegs;
+    SmallSet<Register, 8> GCRegs = collectGCRegs(MI);
     for (unsigned Idx = StatepointOpers(&MI).getVarIdx(),
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I wonder, do we really need to collect GC regs. According to implementation, any register found in operand after some index is considered as GC reg.
So can we just compute this index and use it in this loop.

Do I miss anything?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81647/new/

https://reviews.llvm.org/D81647