[PATCH] D83928: [ARM][TEST] Add a new test case of add-imm & sub-imm on armv6

[Ben Shi via Phabricator via llvm-commits]

benshi001 created this revision.
benshi001 added reviewers: MaskRay, SjoerdMeijer.
Herald added subscribers: llvm-commits, danielkiss, kristof.beyls.
Herald added a project: LLVM.

This case will show furture optimization of add-imm & sub-imm on armv6.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83928

Files:
  llvm/test/CodeGen/ARM/armv6-add-sub-imm.ll


Index: llvm/test/CodeGen/ARM/armv6-add-sub-imm.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/armv6-add-sub-imm.ll
@@ -0,0 +1,58 @@
+; RUN: llc -mtriple=armv6 %s -o - | FileCheck %s --check-prefix=CHECK
+
+; Check how immediates are handled in add/sub on armv6.
+
+define i32 @sub0(i32 %0) {
+; CHECK-LABEL: sub0
+; CHECK:       @ %bb.0:
+; CHECK:       sub r0, r0, #23
+  %2 = sub i32 %0, 23
+  ret i32 %2
+}
+
+define i32 @sub1(i32 %0) {
+; CHECK-LABEL: sub1
+; CHECK:       @ %bb.0:
+; CHECK:       ldr [[R1:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK:       add [[R0:r[0-1]+]], [[R0:r[0-1]+]], [[R1:r[0-1]+]]
+; CHECK:       [[CONST]]
+  %2 = sub i32 %0, 131071
+  ret i32 %2
+}
+
+define i32 @sub2(i32 %0) {
+; CHECK-LABEL: sub2
+; CHECK:       @ %bb.0:
+; CHECK:       ldr [[R1:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK:       add [[R0:r[0-1]+]], [[R0:r[0-1]+]], [[R1:r[0-1]+]]
+; CHECK:       [[CONST]]
+  %2 = sub i32 %0, 2302720
+  ret i32 %2
+}
+
+define i32 @add0(i32 %0) {
+; CHECK-LABEL: add0
+; CHECK:       @ %bb.0:
+; CHECK:       add r0, r0, #23
+  %2 = add i32 %0, 23
+  ret i32 %2
+}
+
+define i32 @add1(i32 %0) {
+; CHECK-LABEL: add1
+; CHECK:       @ %bb.0:
+; CHECK:       ldr [[R1:r[0-1]+]], [[CONST:.[A-Z0-9_]+]]
+; CHECK:       add [[R0:r[0-1]+]], [[R0:r[0-1]+]], [[R1:r[0-1]+]]
+; CHECK:       [[CONST]]
+  %2 = add i32 %0, 131071
+  ret i32 %2
+}
+
+define i32 @add2(i32 %0) {
+; CHECK-LABEL: add2
+; CHECK:       @ %bb.0:
+; CHECK:       add [[R0:r[0-1]+]], [[R0:r[0-1]+]], #8960
+; CHECK:       add [[R0:r[0-1]+]], [[R0:r[0-1]+]], #2293760
+  %2 = add i32 %0, 2302720
+  ret i32 %2
+}


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