[PATCH] D83830: [ARM] VBIT/VBIF support added.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

This looks nice and clean, from what I can tell.



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Comment at: llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp:1868
+        // Expand to VBIT
+        unsigned newOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
+        BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc))
----------------
NewOpc


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Comment at: llvm/lib/Target/ARM/ARMInstrNEON.td:5512
 //              like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
-// FIXME: This instruction's encoding MAY NOT BE correct.
 def  VBIFd    : N3VX<1, 0, 0b11, 0b0001, 0, 1,
----------------
This wasn't true, I guess? Can you make sure we have tests for vbif and vbit encodings, and they look alright. Something in test/MC/ARM and test/MC/Disassembler/ARM.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D83830/new/

https://reviews.llvm.org/D83830