[PATCH] D83830: [ARM] VBIT/VBIF support added.

[Pavel Iliin via Phabricator via llvm-commits]

ilinpv created this revision.
ilinpv added reviewers: dmgreen, SjoerdMeijer, grosbach.
Herald added subscribers: llvm-commits, danielkiss, javed.absar, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Vector bitwise selects are matched by pseudo VBSP instruction
and expanded to VBSL/VBIT/VBIF after register allocation
depend on operands registers to minimize extra copies.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83830

Files:
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/ARM/ARMScheduleR52.td
  llvm/lib/Target/ARM/ARMScheduleSwift.td
  llvm/test/CodeGen/ARM/fcopysign.ll
  llvm/test/CodeGen/ARM/fp16-promote.ll
  llvm/test/CodeGen/ARM/vbsl-constant.ll
  llvm/test/CodeGen/ARM/vbsl.ll
  llvm/test/CodeGen/ARM/vselect_imax.ll
  llvm/test/CodeGen/Thumb2/float-intrinsics-double.ll
  llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll

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