[PATCH] D83602: [DAGCombiner] Scalarize splats with just one demanded lane

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

We've been making progress performing similar ops in the vector-combiner pass based on cost metrics - have you looked at performing it there?

In D83602#2146156 <https://reviews.llvm.org/D83602#2146156>, @tlively wrote:

> Yes, this fixes lowering-produced code. In particular, WebAssembly's vector shift instructions take a scalar shift amount, but in LLVM IR vector shifts take vector shift amounts. WebAssembly's lowering then needs to scalarize the shift entirely except when the shift amount is a splat value, in which case it can just take one lane as the scalar shift amount. This sequence of patches improves codegen in that case.


X86/SSE uses a similar 'vector shift by scalar' approach - and SimlifyDemandedVectorElts etc. manages to remove similar issues - is it possible that WebAssembly is just missing a combine from its shift ops to try and simplify the operands?


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