[PATCH] D83602: [DAGCombiner] Scalarize splats with just one demanded lane
Heejin Ahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 21:18:22 PDT 2020
aheejin added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:17677-17679
+ case ISD::ADD:
+ case ISD::SUB:
+ case ISD::AND: {
----------------
spatel wrote:
> Why only these 3 binops?
> Could this be TLI.isBinOp(Opc) instead?
I was wondering about the same thing. I suspect the author might have tried to match opcodes listed [[ https://github.com/llvm/llvm-project/blob/5282a6186cfb1405756811815a0187c84881baee/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L2313-L2323 | here ]]. But those opcodes in `SelectionDAG::isSplatValue` look like they were selected somewhat arbitrarily in the first place (it says they are "common patterns").
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83602/new/
https://reviews.llvm.org/D83602
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