[PATCH] D83775: [RISCV] add the assemble and disassemble support of Zvlsseg instructions

[Simon Cook via Phabricator via llvm-commits]

simoncook added a comment.

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83775/new/

https://reviews.llvm.org/D83775