[PATCH] D83775: add the assemble and disassemble support of Zvlsseg instructions

[luxufan via Phabricator via llvm-commits]

StephenFan created this revision.
StephenFan added reviewers: asb, HsiangKai.
Herald added subscribers: llvm-commits, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

This implement the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.8 spec version.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83775

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s

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