[PATCH] D83811: [AArch64][SVE] Add support for trunc to <vscale x N x i1>.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: sdesmalen, paulwalker-arm, cameron.mcinally.
Herald added subscribers: danielkiss, psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

This isn't a natively supported operation, so convert it to a mask+compare.

In addition to the operation itself, fix up some surrounding stuff to make the testcase work: we need concat_vectors on i1 vectors, we need legalization of i1 vector truncates, and we need to fix up all the relevant uses of getVectorNumElements().


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83811

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-trunc.ll

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