[PATCH] D83777: [ARM] Generate [SU]HADD from ((a + b) >> 1)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8869
+// shadd(OpA, OpB) from them.
+static SDValue tryLowerToHalvingAdd(SDNode *N, SelectionDAG &DAG) {
+  EVT VT = N->getValueType(0);
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While you're in the area, can you convert this to a TargetDAGCombine?  All the types and operations involved here are legal, so there's no need to mix it up with legalization.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83777/new/

https://reviews.llvm.org/D83777