[PATCH] D83764: DAG: Try scalarizing when expanding saturating add/sub

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked 2 inline comments as done.
arsenm added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7327
 
+  // FIXME: Should really try to split the vector in case it's legal on a
+  // subvector.
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dmgreen wrote:
> Would this ever happen? Having the operation legal on a smaller vector width, without it being legal in the higher size?
Yes, this ends up being the the case for all 16-bit vector operations for AMDGPU (which we just hack around with custom lowering). The vector types are all legal, so they reach the final legalization phase but really need to be split into <2 x i16> operations


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7329
+  // subvector.
+  if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
+    return DAG.UnrollVectorOp(Node);
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dmgreen wrote:
> 64bit VSelect could actually be fine on MVE. Other operations like add and settcc would actually be more trouble.
> Should we at least be testing for something like !isOperationLegalOrCustom(OverflowOp, VT) too?
Tried that first, but didn't work for x86


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  https://reviews.llvm.org/D83764/new/

https://reviews.llvm.org/D83764