[PATCH] D79875: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32Zbt.ll:151
+
+define i64 @fshl_i64(i64 %a, i64 %b, i64 %c) nounwind {
+; RV32I-LABEL: fshl_i64:
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Nitpick: See comment on first patch regarding these extra tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79875/new/

https://reviews.llvm.org/D79875