[PATCH] D83641: [AMDGPU] Apply pre-emit s_cbranch_vcc optimation to more patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp:131
+  } else {
+    assert(false && "Op2 must be register or immediate");
   }
----------------
llvm_unreachable


================
Comment at: llvm/test/CodeGen/AMDGPU/insert-skip-from-vcc.mir:343-344
+# GCN-LABEL: name: andn2_execz_mov_vccz
+# GCN-NOT: S_MOV_
+# GCN-NOT: S_ANDN2_
+# GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
----------------
Negative checks make me nervous. Can you generate these?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83641/new/

https://reviews.llvm.org/D83641