[PATCH] D71767: [POC][SVE] Allow code generation for fixed length vectorised loops [Patch 2/2].

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm updated this revision to Diff 277458.
paulwalker-arm added a comment.
Herald added a subscriber: steven.zhang.

Nothing to see here, just rebasing for those who want to experiment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71767/new/

https://reviews.llvm.org/D71767

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D71767.277458.patch
Type: text/x-patch
Size: 17908 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200713/6be27765/attachment.bin>