[PATCH] D77030: [RISCV] refactor FeatureRVCHints to make ProcessorModel more intuitive
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Thu Jul 9 23:08:03 PDT 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rG04b9a46c842f: [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive (authored by Zakk Chen <zakk.chen at sifive.com>).
Changed prior to commit:
https://reviews.llvm.org/D77030?vs=261187&id=276914#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77030/new/
https://reviews.llvm.org/D77030
Files:
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/MC/RISCV/rv32c-invalid.s
Index: llvm/test/MC/RISCV/rv32c-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv32c-invalid.s
+++ llvm/test/MC/RISCV/rv32c-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=-rvc-hints < %s 2>&1 \
+# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=+no-rvc-hints < %s 2>&1 \
# RUN: | FileCheck %s
## GPRC
Index: llvm/lib/Target/RISCV/RISCVSubtarget.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -54,7 +54,7 @@
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
- bool EnableRVCHintInstrs = false;
+ bool EnableRVCHintInstrs = true;
bool EnableSaveRestore = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -140,12 +140,12 @@
AssemblerPredicate<(all_of FeatureStdExtB),
"'B' (Bit Manipulation Instructions)">;
-def FeatureRVCHints
- : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
- "Enable RVC Hint Instructions.">;
+def FeatureNoRVCHints
+ : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
+ "Disable RVC Hint Instructions.">;
def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
- AssemblerPredicate<(all_of FeatureRVCHints),
- "RVC Hint Instructions">;
+ AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
+ "RVC Hint Instructions">;
def FeatureStdExtV
: SubtargetFeature<"experimental-v", "HasStdExtV", "true",
@@ -207,15 +207,13 @@
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
-def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
+def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
-def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
- FeatureRVCHints]>;
+def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
-def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
+def : ProcessorModel<"rocket-rv32", Rocket32Model, []>;
-def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
- FeatureRVCHints]>;
+def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit]>;
//===----------------------------------------------------------------------===//
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