[PATCH] D79870: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions

[Paolo Savini via Phabricator via llvm-commits]

PaoloS marked an inline comment as done.
PaoloS added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:641
+def SROIPat  : ComplexPattern<XLenVT, 2, "SelectSROI", [or]>;
+def SLOIWPat  : ComplexPattern<XLenVT, 2, "SelectSLOIW", [sext_inreg]>;
+def SROIWPat  : ComplexPattern<XLenVT, 2, "SelectSROIW", [or]>;
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lewis-revill wrote:
> Can these W selects be guarded for 64 bit only?
Not sure how to do it, they can't be enclosed in Predicates like the instruction patterns.


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