[PATCH] D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions
Paolo Savini via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 9 08:37:57 PDT 2020
PaoloS marked an inline comment as done.
PaoloS added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:870
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def : Pat<(or (riscv_sllw (assertsexti32 GPR:$rs1), (assertsexti32 GPR:$rs2)),
----------------
lewis-revill wrote:
> I'm not quite sure given the tests here how these patterns are used? Is `@llvm.fshl.i32` lowered to this pattern?
Precisely.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D79873/new/
https://reviews.llvm.org/D79873
More information about the llvm-commits
mailing list