[PATCH] D79873: [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoB.td:870
 
+let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
+def : Pat<(or (riscv_sllw (assertsexti32 GPR:$rs1), (assertsexti32 GPR:$rs2)),
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I'm not quite sure given the tests here how these patterns are used? Is `@llvm.fshl.i32` lowered to this pattern?


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  https://reviews.llvm.org/D79873/new/

https://reviews.llvm.org/D79873