[PATCH] D81647: MIR Statepoint refactoring. Part 3: Spill GC Ptr regs.
Denis Antrushin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 8 09:56:30 PDT 2020
dantrushin updated this revision to Diff 276470.
dantrushin added a comment.
Add (hand crafted) test for shared landing pad;
Slightly change cache handling code to better handle shared landing pads;
Improve debug output;
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81647/new/
https://reviews.llvm.org/D81647
Files:
llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
llvm/test/CodeGen/X86/statepoint-fixup-call.mir
llvm/test/CodeGen/X86/statepoint-fixup-invoke.mir
llvm/test/CodeGen/X86/statepoint-fixup-shared-ehpad.mir
llvm/test/CodeGen/X86/statepoint-vreg.mir
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