[PATCH] D83137: [SVE][CodeGen] Legalisation of masked loads and stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7135
   if (IsCompressedMemory) {
+    assert(!DataVT.isScalableVector() &&
+           "Cannot currently handle compressed memory with scalable vectors");
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kmclaughlin wrote:
> david-arm wrote:
> > Do we know if this is something we catch earlier and hence should never get here? I just wonder if here it's not really an assert that something went wrong with the code, but perhaps we just hit a case we don't support yet? If it's just because we don't support it yet, instead of asserting we could do:
> > 
> > if (DataVT.isScalableVector())
> >   report_fatal_error("Cannot currently handle compressed memory with scalable vectors");
> I think this is something that we just don't support yet, so I've changed this to `report_fatal_error` as suggested
This is part of the support for llvm.masked.expandload/llvm.masked.compressstore.  There isn't a native instruction for that in SVE, but it's still a reasonable operation with scalable vectors.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1096
 
+  // Extract lo/hi halves of legal predicate types.
+  def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))),
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Do we need to support extracting, for example, an nxv2i1 from an nxv16i1?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83137/new/

https://reviews.llvm.org/D83137